Integrated circuit (IC) devices such as, for example, processors, contain numerous circuit blocks known as buffers. A buffer is a circuit that resides on an interconnect line, and may condition or gale the electrical signal that is sent along the interconnect line. For example, an interconnect line may connect a portion of memory in a processor to the processor's execution unit where mathematical operations are carried out. When the signal is initially sent along the interconnect line from memory, the execution unit may be busy executing other data. In this case, a tristate buffer holds the signal on the interconnect line, preventing the signal from passing through to the execution unit. Once the execution unit is ready to receive the signal, the tristate buffer releases the signal, and the data represented by the signal is then allowed to be transferred to the execution unit. The use of a tristate buffer in this manner preserves the accuracy of the data and serves to organize the flow of data through the processor.
As the speed of ICs increases, it becomes more important to implement buffers that are quick to transfer signals from the buffer input to the buffer output. Implementing fast buffers reduces the signal delay associated with passing the signal through the buffer, thereby increasing the speed of the IC.
FIG. 1 is a circuit diagram of a tristate buffer comprising an n-channel and a p-channel transistor in an inverting configuration wherein the gate of the p-channel transistor is controlled by a NAND gate and the gate of the n-channel transistor is controlled by a NOR gate. The input to the buffer is coupled to an input of NAND gate 103 and NOR gate 104. The clock input to the tristate buffer is coupled to an input of NOR gate 104 and an input of inverter 100, the output from inverter 100 being coupled to NAND gate 103. The output of NAND gate 103 is coupled to the gate of p-channel transistor 101, and the output of NOR gate 104 is coupled to the gate of n-channel transistor 102. The source of p-channel transistor 101 is coupled to the voltage supply, and the drain of transistor 101 is coupled to the output of the buffer. The source of n-channel transistor 102 is coupled to ground, and the drain of transistor 102 is coupled to the output of the buffer. Note that in accordance with transistor nomenclature conventions, the source of a p-channel transistor is defined as the transistor node that is coupled to the voltage supply, and the source of a n-channel transistor is defined as the transistor node that is coupled to ground. In typical semiconductor manufacturing processes, however, the source and drain are symmetrical, and therefore the terms "source" and "drain" are commonly interchangeable.
An inverter inverts the value of the signal applied to its input, and provides the inverted signal at its output. For example, when the input to inverter 100 of FIG. 1 is low (e.g. ground or a predefined logical low value, typically associated with a logical "0" but may be a logical "1" in an inverted logic configuration) the output from inverter 100 is high (e.g. the voltage supply value or a predefined logical high value, typically associated with a logical "1" but may be a logical "0" in an inverted logic configuration). A NAND gate applies a NAND function to its inputs to generate an output, and a NOR gate applies a NOR function to its inputs to generate an output.
When the input to the tristate buffer circuit of FIG. 1 is low, and the clock is low, the output of NAND gate 103 is high and the output of NOR gate 104 is high, thereby turning p-channel transistor 101 off and turning n-channel transistor 102 on. When n-channel transistor 102 is turned on, its drain and source begin to conduct, thereby draining charge from the output line, through transistor 102, to ground, also known as pulling the output down to ground. For this reason, an n-channel transistor in the inverting configuration of FIG. 1 is referred to as a pull-down transistor.
If, instead, the input to the tristate buffer circuit of FIG. 1 is high while the clock is low, the low output of NAND gate 103 turns on p-channel transistor 101, and the low output of NOR gate 104 turns off n-channel transistor 102. When p-channel transistor 101 is turned on, its drain and source begin to conduct, thereby driving charge from the voltage supply onto the output line, through transistor 101, also known as pulling the output up to the voltage supply voltage level. For this reason, a p-channel transistor in the inverting configuration of FIG. 1 is referred to as a pull-up transistor.
Although the input to the tristate buffer of FIG. 1 will be the same value as the output of the buffer during steady state operation, there is some propagation delay associated with pulling the output up or down after the input value switches. Because n-channel transistors in the conduction state (the "on" state) have much lower source-to-drain resistance than p-channel transistors in the conduction state, the output of the buffer or inverter is pulled down much more quickly than it is pulled up. To reduce the pull-up time, a p-channel pull-up transistor is typically made wider than its corresponding n-channel pull-down transistor, thereby reducing the resistance of the p-channel device. Unfortunately, there is an upper limit imposed upon the width of the p-channel transistor because as the p-channel transistor is widened, its gate/source and gate/drain capacitance increases, which has the effect of slowing the switching speed of the p-channel transistor. Eventually, this slower switching speed will dominate and counteract the speed advantages gained by increasing the p-channel device size.
Increasing the p-channel transistor size also uses up valuable semiconductor surface area on the integrated circuit device, thereby increasing manufacturing costs and increasing the size of the IC. In addition, if the resistance on the output line is large enough (e.g. the output line is long), reducing the p-channel transistor resistance by increasing the width will not have a significant impact on reducing the pull-up time because the overall resistance will not be significantly reduced.